Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Signal Integrity Q&A Collection using Keysight ADS

Posted October 21st, 2014 · Please leave a comment · Application Note

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For some time now, my colleague Ming-Chih Lin has been publishing signal integrity tips in question-and-answer format on a the Keysight community forums. Now he has collected all 52 Q&A sheets together the Signal Integrity Q&A Collection using Keysight ADS (Note: It’s a 10 MB PDF so it might take a while to download.)






Here are the details:

Table of Contents

Part 1 Fundamental
SI Matrix
001- I am new to SI simulation. How to start learning SI simulation?
002- What is difference between SERDES and DDR in SI simulation and analysis?
003- What SI analysis approaches does ADS support?
004- What is the difference between pre-simulation and post-simulation?
005- What kind of circuit simulator & EM solver supported by ADS for SI analysis?
ADS Platform
006- What are benefits of ADS platform for SI design and analysis?
007- How to make a complex schematic readable?
008- What is “DesignGuide” and what it can help in signal integrity analysis?
009- What are benefits of ADS data display?
Part 2 Design Cycle
010- What is a “Signal Integrity Design Cycle”?
Modeling
IO Modeling
011- How to import an HSPICE netlist of IO Buffer for SI simulation?
012- How to build SERDES transmitter and receiver Algorithmic Model Interface (AMI) models with SystemVue?
013- How to set up IBIS (Input/Output Buffer Information Specification) models for SI simulation in ADS?
Channel Modeling
014- Could you explain how to model high speed channel? And what I have to pay attention to when modeling a channel?
015- Which components in ADS are used in channel modeling for signal integrity design and analysis?
016- How to design a transmission line in ADS?
017- How to design controlled impedance vias with Via Drawing Utility?
018- What is current return path of a transmission line?
019- How to build a measurement-based channel model?
020- What is “broadband SPICE model” and how to generate it?
EM Modeling
021- What structures in a transmission line cause impedance mismatch?
022- How to Import a PCB layout into ADS layout editor
023- How to perform an Electromagnetic (EM) simulation within ADS?
024- How to define pins and ports in ADS momentum?
025- How to extract an RLC equivalent circuit of a package from S parameters?
026- How to extract S parameters of a high speed connector in EMPro?
027- How to export EMPro simulation results to ADS for SI simulation?
Simulation
028- What is the benefit of S parameter simulation? And what components are specific for S parameter simulation?
029- What components in ADS are used for Transient analysis?
030- What are benefits of ChannelSim? What components in ADS are compatible with ChannelSim?
031- How to set up bit sequence in ADS source components?
032- How to build an optimal and robust high speed digital design?
033- How to perform batch simulation efficiently with Batch Simulation controller?
034- How to examine performance of multi-channels efficiently?
035- How to calculate insertion loss, return loss and crosstalk of differential pairs in mixed mode S parameters?
Analyses
036- Does ADS have signal analyses like those in oscilloscopes?
037- Keysight ENA option TDR is used to convert measured S parameter to TDR. How can I get TDR impedance from an S parameter in ADS?
038- How to debug a SERDES design with jitter analysis?
039- How to export waveform files from ADS to Infiniium for eye and jitter analyses?
040- How to read a waveform file of csv format in ADS for SI analysis?
041- How to build a compliance test report of DDR4 simulation?
Part 3 Applications
SERDES
042- What are architectures of high speed SERDES transmitter and receiver?
043- What is Inter Symbol Interference (ISI)?
044- How does pre-emphasis work to improve a high speed digital signal?
045- How does Continuous Time Linear Equalizer (CTLE) work to improve a high speed digital signal?
046- How does Feed Forward Equalizer (FFE) work to improve a high speed digital signal?
047- How does Decision Feedback Equalizer (DFE) work to improve a high speed digital signal?
Power Integrity
048- What are high frequency characteristics of a real capacitor?
049- How to import vendor component libraries and use those components in a design?
050- How to model a power distribution system?
051- How to analyze impedance of a Power Distribution Network (PDN)?
052- How to select decoupling capacitors to meet target impedance of a PDN efficiently?

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Workshop on IBIS AMI Model Generation – Bangalore – 8th October 2014

Posted October 1st, 2014 · Please leave a comment · Workshop

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We’re offering a hands-on one-day workshop on IBIS AMI model generation in Bangalore, India, 8th October 2014. Registration includes lunch and is free. Simply email prathusha_mathew@non.keysight.com or call +91-80-40148740

Abstract

With increasing data rates of SerDes channels and complexity of the associated digital equalization blocks, classic time-domain simulations with legacy IBIS and SPICE models have slowed to the point where their usefulness is limited. Extremely long simulation times associated with transistor level models and vendor-specific encryption increase the effort required to develop accurate models and decrease model portability. Furthermore, even when such models are developed, simulation throughput is limited and design validation takes a long time. With the release of the IBIS 5.0 in 2008, Algorithmic Modeling Interface (AMI) has provided an Industry- standard way of simulating high-speed serial links with advanced signal processing elements, such as analog filters, FFE and DFE, etc. IBIS-AMI models offer orders-of-magnitude of improvement in simulation time, while IP remains hidden and protected within a compiled executable in binary format called from EDA tools through a standard interface. This standard interface allows AMI models to run on any EDA tools that support IBIS-AMI. With their high flexibility and good IP protection, AMI models have become the choice of many design customers and SerDes vendors.

Take a test drive with Keysight EEsof EDA tools. See how to generate AMI models with easy to use automatic AMI model generation using Keysight SystemVue tool. This complimentary hands-on workshop will give you firsthand experience with the AMI Model Generation and Validation using the power of Keysight EEsof EDA tools

Agenda

8:30 AM Registration (Free)
09:00 AM IBIS-AMI Basics & AMI Modeling Overview
10:00 AM Hands-on Session- Case Study 1: USB 3.0 Transmitter AMI Model Generation
12:30 PM Lunch
1:30 PM Hands-on Session- Case Study 2: USB 3.0 Receiver AMI Model Generation
4:00 PM Hands-on Session: AMI Model Validation using Keysight ADS
4:30 PM Summary and Q&A

Who should attend

Engineers responsible for generating and validating AMI models for High Speed SERDES applications like HDMI, USB, PCIe, etc

Date and Location

8th October 2014
Keysight Technologies India Pvt Ltd.
The Millenia, Second Floor, Tower D,
1 and 2 Murphy Road, Ulsoor,
Bangalore – 560008

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Webcast: How to Optimize Your SerDes Design During the Pre-layout Phase

Posted September 17th, 2014 · Please leave a comment · Webcast

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I’m giving a webcast next week entitled How to Optimize Your SerDes Design During the Pre-layout Phase followed by an interactive Q&A. Click on the title link for free registration.

Date & time: Thursday, September 25, 2014 at 10am US Pacific Time / 1pm US Eastern Time

Abstract:

In the era of receiver equalization, older stackup and controlled impedance line design tools are obsolete because the metrics they output (frequency response) are irrelevant. The metric that matters today is the post-equalization eye opening. In this webcast we will show you how to optimize the pre-layout design using a PCI Express transmitter, channel, and receiver as an example.

Hope to see you there!

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