Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

Signal Integrity header image 1

DesignCon 2015 Papers

Posted February 10th, 2015 · Please leave a comment · Technical Paper


Here are the papers from DesignCon 2015 that have one or more Keysight EEsof EDA co-author:

  • With Xilinx: Ultrascale DDR4 De-emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification Paper Slides
  • With Xilinx: IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems Paper Slides
  • With Xilinx and John Baprawski Consulting: A New Methodology for Developing IBIS-AMI Models Paper Slides
  • With Speeding Edge and Wild River Technology: Breaking the 32 Gb/s Barrier: PCB Materials, Simulations, and Measurements Tutorial slides
  • With industry panelists, moderated by Martin Rowe: Closing The Loop: What Do We Do When Measurement & Simulations Don’t Match? Panel discussion

Thanks to our customer co-authors for working with us on these projects!

→ No CommentsTags:

Live Webcast Tomorrow: PCB Materials, Simulations, and Measurements for 32 Gb/s

Posted January 21st, 2015 · Please leave a comment · Webcast

Free registration for PCB Materials, Simulations, and Measurements for 32 Gb/s

My colleague Heidi Barnes is giving a webcast tomorrow titled PCB Materials, Simulations, and Measurements for 32 Gb/s with Lee Ritchey of Speeding Edge and Al Neves of Wild River Technology. Here is the abstract:


Breaking the 32 Gb/s barrier for printed circuit board (PCB) channels requires a strong understanding of PCB stack-up design, simulation methods, and measurement techniques. How a PCB fabrication document calls out the materials, such as fiber weave and surface roughness, is critical to high speed performance. Accuracies of channel performance time and frequency domain simulations at the higher data rates require knowledge of as-fabricated material properties and tolerances. Design and measurement of test structures to validate the PCB stack-up performance require custom fixtures and implementation of high frequency calibration techniques, such as fixture removal. Understanding the basic flow and interaction of stack-up design, simulation, and measurement is critical for leverage of existing low cost PCB manufacturing technology for repeatable design performance. This webcast brings together experts in each of these three areas to demonstrate the basic flow of successful stack-up design with robust correlation between measurements and simulations at 32 Gb/s and beyond.

Hope to see you there!

Free registration for PCB Materials, Simulations, and Measurements for 32 Gb/s

→ No CommentsTags:

Signal Integrity Q&A Collection using Keysight ADS

Posted October 21st, 2014 · Please leave a comment · Application Note


For some time now, my colleague Ming-Chih Lin has been publishing signal integrity tips in question-and-answer format on a the Keysight community forums. Now he has collected all 52 Q&A sheets together the Signal Integrity Q&A Collection using Keysight ADS (Note: It’s a 10 MB PDF so it might take a while to download.)

Here are the details:

Table of Contents

Part 1 Fundamental
SI Matrix
001- I am new to SI simulation. How to start learning SI simulation?
002- What is difference between SERDES and DDR in SI simulation and analysis?
003- What SI analysis approaches does ADS support?
004- What is the difference between pre-simulation and post-simulation?
005- What kind of circuit simulator & EM solver supported by ADS for SI analysis?
ADS Platform
006- What are benefits of ADS platform for SI design and analysis?
007- How to make a complex schematic readable?
008- What is “DesignGuide” and what it can help in signal integrity analysis?
009- What are benefits of ADS data display?
Part 2 Design Cycle
010- What is a “Signal Integrity Design Cycle”?
IO Modeling
011- How to import an HSPICE netlist of IO Buffer for SI simulation?
012- How to build SERDES transmitter and receiver Algorithmic Model Interface (AMI) models with SystemVue?
013- How to set up IBIS (Input/Output Buffer Information Specification) models for SI simulation in ADS?
Channel Modeling
014- Could you explain how to model high speed channel? And what I have to pay attention to when modeling a channel?
015- Which components in ADS are used in channel modeling for signal integrity design and analysis?
016- How to design a transmission line in ADS?
017- How to design controlled impedance vias with Via Drawing Utility?
018- What is current return path of a transmission line?
019- How to build a measurement-based channel model?
020- What is “broadband SPICE model” and how to generate it?
EM Modeling
021- What structures in a transmission line cause impedance mismatch?
022- How to Import a PCB layout into ADS layout editor
023- How to perform an Electromagnetic (EM) simulation within ADS?
024- How to define pins and ports in ADS momentum?
025- How to extract an RLC equivalent circuit of a package from S parameters?
026- How to extract S parameters of a high speed connector in EMPro?
027- How to export EMPro simulation results to ADS for SI simulation?
028- What is the benefit of S parameter simulation? And what components are specific for S parameter simulation?
029- What components in ADS are used for Transient analysis?
030- What are benefits of ChannelSim? What components in ADS are compatible with ChannelSim?
031- How to set up bit sequence in ADS source components?
032- How to build an optimal and robust high speed digital design?
033- How to perform batch simulation efficiently with Batch Simulation controller?
034- How to examine performance of multi-channels efficiently?
035- How to calculate insertion loss, return loss and crosstalk of differential pairs in mixed mode S parameters?
036- Does ADS have signal analyses like those in oscilloscopes?
037- Keysight ENA option TDR is used to convert measured S parameter to TDR. How can I get TDR impedance from an S parameter in ADS?
038- How to debug a SERDES design with jitter analysis?
039- How to export waveform files from ADS to Infiniium for eye and jitter analyses?
040- How to read a waveform file of csv format in ADS for SI analysis?
041- How to build a compliance test report of DDR4 simulation?
Part 3 Applications
042- What are architectures of high speed SERDES transmitter and receiver?
043- What is Inter Symbol Interference (ISI)?
044- How does pre-emphasis work to improve a high speed digital signal?
045- How does Continuous Time Linear Equalizer (CTLE) work to improve a high speed digital signal?
046- How does Feed Forward Equalizer (FFE) work to improve a high speed digital signal?
047- How does Decision Feedback Equalizer (DFE) work to improve a high speed digital signal?
Power Integrity
048- What are high frequency characteristics of a real capacitor?
049- How to import vendor component libraries and use those components in a design?
050- How to model a power distribution system?
051- How to analyze impedance of a Power Distribution Network (PDN)?
052- How to select decoupling capacitors to meet target impedance of a PDN efficiently?

→ No CommentsTags: