Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Workshop on IBIS AMI Model Generation – Bangalore – 8th October 2014

Posted October 1st, 2014 · Please leave a comment · Workshop


We’re offering a hands-on one-day workshop on IBIS AMI model generation in Bangalore, India, 8th October 2014. Registration includes lunch and is free. Simply email or call +91-80-40148740


With increasing data rates of SerDes channels and complexity of the associated digital equalization blocks, classic time-domain simulations with legacy IBIS and SPICE models have slowed to the point where their usefulness is limited. Extremely long simulation times associated with transistor level models and vendor-specific encryption increase the effort required to develop accurate models and decrease model portability. Furthermore, even when such models are developed, simulation throughput is limited and design validation takes a long time. With the release of the IBIS 5.0 in 2008, Algorithmic Modeling Interface (AMI) has provided an Industry- standard way of simulating high-speed serial links with advanced signal processing elements, such as analog filters, FFE and DFE, etc. IBIS-AMI models offer orders-of-magnitude of improvement in simulation time, while IP remains hidden and protected within a compiled executable in binary format called from EDA tools through a standard interface. This standard interface allows AMI models to run on any EDA tools that support IBIS-AMI. With their high flexibility and good IP protection, AMI models have become the choice of many design customers and SerDes vendors.

Take a test drive with Keysight EEsof EDA tools. See how to generate AMI models with easy to use automatic AMI model generation using Keysight SystemVue tool. This complimentary hands-on workshop will give you firsthand experience with the AMI Model Generation and Validation using the power of Keysight EEsof EDA tools


8:30 AM Registration (Free)
09:00 AM IBIS-AMI Basics & AMI Modeling Overview
10:00 AM Hands-on Session- Case Study 1: USB 3.0 Transmitter AMI Model Generation
12:30 PM Lunch
1:30 PM Hands-on Session- Case Study 2: USB 3.0 Receiver AMI Model Generation
4:00 PM Hands-on Session: AMI Model Validation using Keysight ADS
4:30 PM Summary and Q&A

Who should attend

Engineers responsible for generating and validating AMI models for High Speed SERDES applications like HDMI, USB, PCIe, etc

Date and Location

8th October 2014
Keysight Technologies India Pvt Ltd.
The Millenia, Second Floor, Tower D,
1 and 2 Murphy Road, Ulsoor,
Bangalore – 560008

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Webcast: How to Optimize Your SerDes Design During the Pre-layout Phase

Posted September 17th, 2014 · Please leave a comment · Webcast


I’m giving a webcast next week entitled How to Optimize Your SerDes Design During the Pre-layout Phase followed by an interactive Q&A. Click on the title link for free registration.

Date & time: Thursday, September 25, 2014 at 10am US Pacific Time / 1pm US Eastern Time


In the era of receiver equalization, older stackup and controlled impedance line design tools are obsolete because the metrics they output (frequency response) are irrelevant. The metric that matters today is the post-equalization eye opening. In this webcast we will show you how to optimize the pre-layout design using a PCI Express transmitter, channel, and receiver as an example.

Hope to see you there!

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Summer Hiatus and Transition to Keysight

Posted July 16th, 2014 · Please leave a comment · Notice


Please note that my blog will be on hiatus from now until mid-August for the big, exciting transition from Agilent EEsof EDA in the Electronic Measurement Group of Agilent to our new name Keysight EEsof EDA. In anticipation of this transition, please bookmark the new URL:
…which is now live. I apologize in advance for any outages during the migration.

We have a lot of good things planned so I hope to see you there!

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