Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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How to Use Fixture De-embedding to Match Signal Integrity Simulations to Measurements

Posted April 30th, 2015 · Please leave a comment · Video

My colleague Heidi Barnes has published a great video and a download on “How to Use Fixture De-embedding to Match Signal Integrity Simulations to Measurements.” Both the video and the download link are posted on our YouTube channel: These tools show how to correlate simulation and measurement with a focus on the critical step of either de-embedding the fixture from the measurement, or alternatively embedding a fixture model into the simulation. Useful tips. Thanks, Heidi!

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Order Your Free DVD of the DesignCon Keysight Education Forum

Posted April 21st, 2015 · 1 Comment · Seminar, Video

At DesignCon we presented the Keysight Education Forum. The talks are now available on a free DVD. Order yours today while supplies last!

DesignCon 2015 Keysight Education Forum DVD

DesignCon 2015 Keysight Education Forum DVD

The ten presentations are:

  • USB 3.1 Gen 2 (10 Gbps) Physical Layer Test Challenges
  • Practical Guide to Quickly Making 100G Electrical Measurements
  • PCIe protocol analysis for SSDs
  • Power Integrity Solution – Choosing the Right Measurement and Simulation Tools
  • DDR4/LPDDR4: Overcome the Barriers of Simulating, Testing and Probing High-Speed Memory Systems
  • Tips and Techniques to Characterize Signal Integrity Problems Quickly and Accurately
  • Simulation and Characterization of PAM-4 signals in 28G and 56G Designs
  • Gain Insight into DDR3/4 and LPDDR3/4
  • Surmounting the Challenges of 16 Gigabit Operation with PCI Express Rick Eads
  • Addressing the challenges of PAM-4 receiver stressed input testing

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DesignCon 2015 Papers

Posted February 10th, 2015 · Please leave a comment · Technical Paper


Here are the papers from DesignCon 2015 that have one or more Keysight EEsof EDA co-author:

  • With Xilinx: Ultrascale DDR4 De-emphasis and CTLE Feature Optimization with Statistical Engine for BER Specification Paper Slides
  • With Xilinx: IBIS-AMI Modeling and Simulation of 56G PAM4 Link Systems Paper Slides
  • With Xilinx and John Baprawski Consulting: A New Methodology for Developing IBIS-AMI Models Paper Slides
  • With Speeding Edge and Wild River Technology: Breaking the 32 Gb/s Barrier: PCB Materials, Simulations, and Measurements Tutorial slides
  • With industry panelists, moderated by Martin Rowe: Closing The Loop: What Do We Do When Measurement & Simulations Don’t Match? Panel discussion

Thanks to our customer co-authors for working with us on these projects!

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