Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

Signal Integrity header image 2

Free Agilent Event – Interconnect Analysis & Modeling Workshop

Posted September 10th, 2008 · Please leave a comment · Workshop


We’re offering two free, half-day, hands-on events:

Interconnect Analysis & Modeling Workshop

Both sessions are on September 22, 2008 at Agilent Technologies, 5301 Stevens Creek Blvd, Santa Clara CA

1) Morning session is 8:00am – noon

2) Identical afternoon session is 12:45pm – 4:45pm

Seating is limited, so early registration is advised.

More details and registration at:


The workshop will start with a presentation reviewing the measurement and simulation technologies, approaches and case studies. Attendees will then break into smaller groups and rotate through hands-on labs focusing on these topics:

Measurement Lab:

Review a TDR and VNA, discuss TDR and VNA calibration techniques, perform a multi-port calibration, review PLTS automation capabilities, make differential measurements, interpret time and frequency domain results, understand differential S-parameters, and create data file for ADS use.

Simulation Lab:

Review ADS environment, incorporate measured data in a circuit, perform a circuit simulation, interpret simulation results, review “scope” display mode, create an equivalent circuit model for backplane, optimize model to match measured results, explore what-ifs, and review advanced ADS features.

Hope to see you there!

Tags: ···

Please leave the first comment so far ↓

Please leave the first comment.

Leave a Comment