Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Efficient FPGA Transceiver-based Channel Modeling Using Agilent ADS

Posted May 28th, 2008 · 1 Comment · Webcast


Register for “Efficient FPGA Transceiver-based Channel Modeling Using Agilent ADS”.

Free 1-hour live webcast begins 10:00 am PDT 26 June 2008 (1:00 pm EDT, 17:00 GMT)

Sanjeev Gupta (Agilent) and Salman Jiva (Altera)


With FPGAs so commonly used in high-speed designs, signal integrity issues can be minimized by properly modeling the signal path. This presentation will model real world circuit boards using S-parameters, showing that it is possible to predict eye opening performance before a system is physically prototyped. Both extracted and measured models for interconnects will be used. A 90nm transceiver model is incorporated in Agilent ADS as a new library element, permitting system level modeling of interconnects and FPGA transceivers. Both measured and modeled results are shown and the correlation is discussed, concluding that the new method is both execution time efficient and is sufficiently accurate to provide a high level of confidence for designers wishing to design serial links to 6.375 Gb/s.

Altera Stratix II transceiver library download info.

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