Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Hands-on Signal Integrity PCI Express Workshop

Posted July 21st, 2008 · Please leave a comment · Workshop



At multigigabit per second data rates and with channel flight times longer than a bit period, signal integrity is a major concern. Under these conditions, high-speed analog effects, previously only seen in high frequency RF and microwave engineering, can impair the signal quality and degrade the bit error rate of the link. This complementary hands-on workshop will show you how use Advanced Design System (ADS) to dramatically reduced product design cycles by resolving these issues early in the design cycle.

Using PCI Express serial link as an example, we’ll illustrate how you can:

  • Analyze complete serial links by co-simulating individual components, each at its most appropriate level of abstraction: link-, circuit- or physical-level.
  • Import S-parameter backplane and interconnect models accurately into transient (SPICE) simulations.
  • Perform jitter diagnosis with the proven EZJIT Plus algorithm used in Agilent instruments.

Dates for the US leg of the tour:

  • July 29th, 2008 — Austin, TX
  • July 30th, 2008 — Richardson, TX
  • July 31st, 2008 — Santa Clara, CA
  • August 5th, 2008 — Allentown, PA
  • August 5th, 2008 — Andover, MA
  • August 7th, 2008 — Cary, NC
  • August 14th, 2008 — Naperville, IL
  • August 18th, 2008 — Chandler, AZ
  • August 20th, 2008 — Loveland, CO


  • 9:30 – 10:00 — Registration and Continental Breakfast
  • 10:00 – 12:00 — Hands-on workshop: Signal Integrity Design, Analysis and Verification
  • 12:00 – 1:00 — Lunch
  • 1:00 – 3:00 — Workshop continued


Register for Hands-on Workshop: Signal Integrity Design, Analysis, and Verification, July 29th — August 7th, 2008

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