Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Hands-on Workshops: ADS Channel Simulator, DDR3 Compliance, and More!

Posted August 26th, 2009 · 8 Comments · Workshop

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Update March 15, 2012: The material was updated for a series of workshops in 2011. The material was moved here: Successful High Speed Digital Design with ADS, EMPro, and SystemVue

We’re offering five complementary signal integrity hands-on workshops entitled “Design Using Fast Channel Simulation and Statistical Eye Diagrams.” Seating is limited for these complimentary events. Early enrollment is advised.

Why this workshop is important

Signal integrity engineers need to determine ultralow BER contours for thousands of points in the design space in order to select the optimum set of characteristics for transmitter, channel, and receiver. Traditional techniques consume a prohibitively long simulation time. For this reason we’ve implemented a new statistical mode in our Channel Simulator that eliminates the need for long, multi-million-bit simulations. Now you can generate eye diagrams with ultralow BER contours in just a few seconds.

This in-depth hands-on workshop will demonstrate the “what if” design space exploration workflow using our new statistical eye diagram channel simulator, and will also cover tools and modes that can be used in exceptional cases (e.g. equalizer adaptation, non-linearity, or specific bit patterns) where statistical eye techniques cannot be applied.

You will get first hand experiencing using signal integrity features that are new in ADS 2009 Update 1 and EMPro 2009, including equalizers, DDR compliance toolkit, and via simulation with 3DEM.

Who should attend this workshop

Signal integrity engineers for multigigabit links who are running into effects previously only seen in RF and microwave circuits.

Dates & Locations

September 15, 2009 – Ottawa, ON
September 22, 2009 – Chelmsford, MA
September 24, 2009 – Minneapolis, MN
Full! – September 29, 2009 – Santa Clara, CA – Original date – Full!
September 30, 2009 – Santa Clara, CA – Additional date!
October 1, 2009 – Santa Clara, CA – Additional date!
November 4, 2009 – Anaheim, CA – Rescheduled date
November 12, 2009 – Richardson, TX – Additional date!
November 18, 2009 – Austin, TX – Additional date!

Agenda

All times are local
9:30a.m. – Register/Breakfast
10:00a.m. – Part 1

  • ADS for signal integrity analysis
  • HSPICE netlist including W-element in ADS
  • Modeling and simulation of a PCI Express Gen2 channel using Channel Simulator in:
    • Bit by bit mode
    • Statistical mode
  • Equalizer, LMS, RLS, and ZF, and equalizer tap coefficient calculation
12:00p.m. – Lunch
1:00p.m. – Part 2
  • Channel optimization for eye diagram and BER
  • HDMI transmitter and how it can be modeled in ADS
  • DDR Compliance Toolkit
  • 3DEM simulation of a via model with EMPro
3:00p.m. – End
Enroll today!

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