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Meet Us IRL (In Real Life) at DesignCon 2009

Posted January 15th, 2009 · Please leave a comment · Conference

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Despite rumors from some Web 2.0 fanatics that it isn’t necessary, you can still actually meet people “IRL” (in real life) not just virtually via the web. My Agilent colleagues and I will be staffing Booth #305 at DesignCon 2009, in Santa Clara CA, Feb 2-5 2009. Stop by and say hello!

PS:

Click here to vote for my video entry to the DesignCon viral video contest!

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"Day in the Life of an Agilent EEsof EDA Chiphead®". Is there really an upcoming ISO 1984 standard? Find out in this (hopefully) hilarious parody of a famous series of YouTube videos.

PPS: Here are the Agilent papers, workshop, and panels. Example: “7-TA2” means track 7, Tuesday AM, paper 2.

Papers

  • 7-TA2: “Practical Analysis of Backplane Vias for 5 Gbps and Above”, Eric Bogatin (Bogatin Enterprises – BeTheSignal.com), Sanjeev Gupta (Agilent EEsof EDA), Mike Resso (Agilent instruments)
  • 8-TA1: “The use of Optimization in Signal Integrity performance Centric High Speed Digital Design Flows”, Brahim Bensalem (Intel), Sanjeev Gupta (Agilent EEsof EDA)
  • 8-TA3: “Analysis of Random Noise and the Effect of Band-Limited Noise on Stressed-Eye Receiver Tolerance Test”, Ransom Stephens, Marcus Mueller (Agilent instruments)
  • 13-TA4: “Verify your signal integrity margins: De-embedding of fixtures and probing in a real time digital oscilloscope”, Jim Choate (Agilent instruments)
  • 12-WA2: “VNA Characterization of Cable Assemblies for Supercomputer Applications”, Greg Edlund (IBM), Mike Resso (Agilent instruments)
  • 12-WA3: “Characterizing Non-Standard Impedance Channels with 50 Ohm Instruments”, Julian Ferry (Samtec), Mike Resso (Agilent instruments), OJ Danzy (Agilent instruments)
  • 7-WA4: “BER Performances for High-Speed Serial Link System Estimated by using Quasi-Analytical Method”, Ding-qing Lu (Agilent EEsof EDA)
  • 12-THA2: “A Comparison of Fixture Removal Methods for Characterization of Differential PCB Channels”, Weiping Hou (Huawei), Quan-Li Li (Agilent China)

Workshop

Panels

  • TP-MP: “The case of the closing eye – Addressing the Industry’s Next Gen Serial Data Design Validation Challenges”, Panelists include Karl Kachigan (Agilent instruments)
  • TP-WP: “Do it right or do it over? Signal integrity engineer in the era of highly compressed project schedules”, Panelist include Larry Lerner (CTO, Agilent EEsof EDA), Wh

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