Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Posted August 19th, 2009 · Please leave a comment · Application Note

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(Updated Jan 3rd 2010 to note the Jan 12th publication of The New Rules of Marketing and PR: How to Use Social Media, Blogs, News Releases, Online Video, and Viral Marketing to Reach Buyers Directly, 2ed.)

Cover of The New Rules of Marketing and PR book

A big “Thank you!” to published author and marketing speaker David Meerman Scott for holding up my blog (in his words) “as a great example others can learn from.” this blog on pages 250-252 of the second edition of his book The New Rules of Marketing and PR: How to Use Social Media, Blogs, News Releases, Online Video, and Viral Marketing to Reach Buyers Directly, 2ed. If you came here from David’s blog or book, you might be wondering what signal integrity is all about.

Well, if you bought a PC in the mid-1980’s you might remember the clock speed was around 6 MHz (6 million machine processing cycles per second) and the fastest connection to — say — an external disk drive was maybe eight million bytes a second. At those speed the wires joining the chips didn’t degrade the signal between the chips very much and all was well with the world.

Nowadays, the processor is cranking through two or three billion machine processing cycles per second and SuperSpeed USB connectivity at five billion bits per second is on the horizon. At these speeds, a chip-to-chip interconnecting wire only a few inches long can degrade the signal to the point of failure. Signal integrity engineering is about designing the connections in such a way that your PC, your cable modem, and Internet connection works correctly.

So if your PC is working well, thank a signal integrity engineer. If not, then blame Microsoft. 🙂

David delivering the keynote speech at the BMA

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