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Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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ADS Signal Integrity User Group Lunch and Learn – Andover MA – Sept 28, 2010

Posted September 9th, 2010 · Please leave a comment · Seminar

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Updated October 4, 2010: On-demand SD and HD versions of Hermann Ruckerbauer’s paper How to get the most from ADS, the Swiss army knife of high speed digital EDA tool is now posted here:


If you are in the Greater Boston area, I hope you’ll enroll now and join us for an ADS Signal Integrity User Group Lunch and Learn.

This ADS Signal Integrity User Group Lunch and Learn is a forum for Boston Metro area high speed digital engineers to share their experience in using ADS for signal and power integrity design. There will be a mixture of customer papers, informal networking, and discussion.

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Date and Location

Tuesday, September 28

Agilent Technologies, Boston/Chatham Light Rooms, 40 Shattuck Road, Andover, MA 01810

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Agenda

  • Registration (9:45a-10:00a)
  • Paper 1: How to get the most from ADS, the Swiss army knife of high speed digital EDA tools (10:00a-noon)
  • Networking Lunch with ‘scope demo (noon-1:00p)
  • Paper 2: What’s New from EEsof for High Speed Digital? (1:00p-2:00p)
  • Q&A/Close (2:00p-2:30p)

Abstracts

Paper 1: How to get the most from ADS, the Swiss army knife of high speed digital EDA tool

Presenter: Hermann Ruckerbauer, Eye Know How, Munich, Germany

Cobbling together a collection of point tools creates an error prone and inefficient high speed digital design flow. Fortunately there’s no need to do that because ADS provides all required features in one package. This presentation gives overview of how Eye Know How, my consultancy in Germany, uses ADS. Examples will include:

  • Time-domain circuit simulation including the on Multilayer Models transmission line library
  • Data analysis with built-in and custom-coded functions (incl. FP Eye)
  • Layout-based simulations with Momentum (including the Allegro DFI link)
  • Optimizing 3D structures including vias with the EMPro FEM Element
  • Using the SP-TDR front panel for optimization

Even this is already shows a quite large number of features this is only a small part of functions that are provided by ADS.

Lunchtime Demo: See The world’s fastest real-time oscilloscope in action. Agilent’s Infiniium 90000 X-Series. Engineered for 32 GHz true analog bandwidth!

Paper 2: What’s New from EEsof for High Speed Digital?

Presenters: Jason Boh and Colin Warwick

In this paper we’ll give an update of the EEsof products for two high speed digital work flows.

The first is SI/PI PCB design using ADS extended with EMPro. ADS 2011.01 is scheduled for general release in early 2011 and will include a new version of Transient Convolution Simulator with IBIS AMI simulation and a new version of Momentum with power integrity capabilities. We’ll also highlight how EMPro extends ADS.

The second flow is rather different and new. Increasing SERDES vendors are finding encrypted SPICE models of today’s complex multi gigabit transceivers are too slow for their OEM customers to use when doing ‘what if’ design space exploration. IBIS AMI reduces the time taken to evaluate a point in the design space from hours with SPICE to seconds with the statistical mode of Channel Simulator. But how to generate AMI models? Do you spend the time to cultivate the C coding expertise in house? Or turn over your IP and dollars to a specialized consultancy? With SystemVue 2010.07 you have a better path. The IBIS AMI model is a side benefit of an ESL flow that not only allows optimization of the signal processing in a modern data flow tool, but also automatically generates the AMI model from the optimized executable specification that the implementation was based on. You get a better design in a shorter time.

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