Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Article Demystifies IBIS AMI Model Generation

Posted November 3rd, 2010 · 1 Comment · Article

My colleagues Sanjeev Gupta, José Luis Pino, and Amolak Badesha have published an article in EETimes EDA DesignLine entitled AMI models: What, why and how?

It highlights our SystemVue solution which enables IC vendors who are designing multigigabit SERDES to build, verify, and share an IC model of their chip’s I/O receiver and transmitter with their OEM customers.

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