Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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High Speed Digital Seminar – Bangalore India

Posted September 15th, 2010 · Please leave a comment · Seminar

Agilent Technologies India invites you to attend Agilent High Speed Signal Integrity Design, Test and Measurement Seminar as per the details given below.

Why is the Seminar important?

Today’s designs feature high-speed serial I/O technologies like PCI EXPRESS, Fiber Channel, SATA, LVDS, HDMI, Ethernet, XAUI, DDR2, DDR3 etc., with data rates in Gigabit per second, embedded clocks, differential signaling, and layout density that make probing difficult. High-frequency effects from interconnects – traces, vias, connectors, cables, etc. – can significantly impact your design. Knowing how to use the latest tools can accelerate the design and validation process to help you get your products to market faster. At this event, you’ll learn about key test and simulation tools that enable designers to include interconnect effects in their simulations to predict how their design performs before building it.

Who should attend?

This seminar will be valuable to Hardware Design Engineers, System Architects, System designers, Board design Engineers, Layout Engineers, Post Silicon Validation Engineers, Engineering managers, involved with design and testing of high-speed memory, I/O, or other serial communication technologies.

What to expect?

To be successful in creating designs with today’s high-speed data rate serial standards, you need to include the effects of impedance in your design simulations. These include chip-to-chip interconnects on the board, vias, connectors, cables, and backplanes. This requires the designers to combine the digital and RF effects in an analog simulator that includes interconnect models. This seminar will illustrate how to handle various complex design issues and use simulation tools to better understand and troubleshoot your high speed design as well as to deal with some of the complex measurements and standards compliance applications. The seminar will have combination of presentation and variety of live demos on design software and measurement instruments by Agilent technical experts. Agilent technical experts and application engineers will also be available for informal discussions about your unique application.

Where and when will the symposium be held?

Date Venue
October 5th, 2010 Hotel Le Meridien, Bangalore
Agenda
Time Sessions
0900 – 0930 Registrations
0930 – 0945 Welcome and Introduction
0945 – 1030 Analyzing for better noise/jitter margins with ever shrinking eyes in High speed serial bus technologies
1030 – 1130 IBIS AMI modeling and Channel Simulation for High Speed SI applications
1130 – 1200 Tea/Coffee Break and Exhibition
1215 – 1300 Signal Integrity Design using Channel Analysis and EM CoDesign
1300 – 1400 Lunch and Product Fair
1400 – 1500 Integrating EM Simulation in High Speed Design Flow
1500 – 1545 Simplified Physical Layer Receiver Test of Re-timing Architectures Such as USB 3.0, SATA, SAS, PCIe2
1545 – 1600 Tea/Coffee Break and Exhibition
1600 – 1645 LIVE Demonstrations
1645 – 1715 Wrap up and Lucky Draw
How to Register:
Seating is limited for this complimentary seminar. Early registration is advised. To register:
Please call: 1800 11 2929 (toll free) or 0124 229 2009
E-mail: tm_india@agilent.com
Fax: 1800 11 3035 (toll free) or 0124 229 2011
Looking forward to your participation in the seminar,
Thank you
Gautam Awasthi
General Manager – Marketing

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