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Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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IBIS AMI Model Generation, Simulation, and Validation

Posted June 4th, 2010 · Please leave a comment · Seminar


If you have an interest in learning about the latest developments from us here at Agilent in the area of automatic generation of IBIS AMI models and the simulation of those models in high speed SERDES channel simulation, then please click on the link below to sign up for this free technical seminar. Seating is limited so please register early. We will be hosting this half-day seminar twice (June 16 and June 17, 2010) at the Agilent office in Santa Clara. I hope you’ll come to this brand new technical seminar so you can come see the latest developments in IBIS AMI modeling, simulation, and validation .

Enroll for IBIS AMI Model Generation, Simulation, and Validation using Agilent SystemVue, ADS and Oscilloscopes

Dates: Wednesday, June 16 2010 with a repeat on Thursday, June 17 2010

Location: Agilent Technologies office on Stevens Creek Boulevard, Santa Clara, CA


  • 9:30am to 10am – IBIS AMI Model Overview – Amolak Badesha
  • 10am to 11am – Automatic IBIS AMI Model Generation with SystemVue – Jose Pino
  • 11am to Noon – Channel and Link Simulation in ADS with AMI Model – Nilesh Kamdar
  • Noon to 12:30pm – Lunch
  • 12:30pm to 2pm – SERDES Validation with Simulation and Measurement Links – Jeff Cuyle & Amolak Badesha


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