Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Statistical Simulation

Posted February 9th, 2010 · 1 Comment · Guest Post


My thanks to Chad Morgan (Principal Engineer, Circuits & Design, at Tyco Electronics) for permission to upload his DesignCon 2010 paper 7-TH3 here. It’s 2.4MB, so first here’s a quick preview:

Chad’s video interview at Real Time With DesignCon.


Because today’s high-speed, high-density backplane and I/O interconnects are pushing speeds well beyond 10 Gbps, accurate simulation of such systems requires the inclusion of long bit patterns, jitter, equalization, and crosstalk. To include these criteria and increase simulation speed, digital designers are migrating from traditional SPICE and convolution simulations to faster quasi-analytical or statistical simulations when possible. This paper will examine correlation between public-domain tools, EDA vendor tools, and test data using various highspeed interconnects as case studies. The paper will summarize how well simulation tools optimize equalization and predict system performance to low probability levels.

DesignCon 2010 7-TH3 Figure 11

Figure 11: Measured (white) and Simulated (blue) De-emphasized Eye Pattern at 6.25 Gbps through Test Cables. As Figure 11 shows, when using the same tap values for both measurement and simulation, correlation is excellent. Both de-emphasized waveforms show a similar rise-time, and both methods keep the same rise-time for both full-swing and partial-swing bits in the pattern.

Download the PDF

Validation of Quasi-Analytical and Statistical Simulation Techniques for Multi-Gigabit Interconnect Channels

Thanks again, Chad!

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