Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Interview and Webcast Series

Posted December 8th, 2011 · Please leave a comment · Webcast

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If you can’t get enough of me here on my blog, then surf on over to EE Web. They interviewed me for their “Featured Engineer” series. The interview is posted here:

Featured Engineer: Colin Warwick

Let me know what you think?

Also, I’m presenting the first of a series of three webcasts. The second and third will be presented by my colleagues Sanjay Sethi and Hany Fahmy. You can sign up for all three here:

Overcome High Speed Digital Design Challenges Webcast Series

Series Abstract

When digital signals reach gigabit/s speeds, the unpredictable becomes the norm. The process of getting your project back on track starts with the best tools for the job. You’ll need techniques taken from communication science (like adaptive equalization) and tools taken from microwave engineering (like field solvers) to overcome the three main design challenges: signal integrity, power integrity, and EMI/EMC. In this series of webcasts we’ll show you how to improve time-to-market by proactive application of these modern techniques.

Webcast 1: Overcome Signal Integrity Challenges in the Multigigabit/s Era

December 15, 2011

First Session: 7AM PT/10AM ET/3PM GMT/16:00 CET

Second Session: 10AM PT/1PM ET/6PM GMT/19:00 CET

To mitigate channel impairments in the multigigabit/s regime, modern SERDES employ signal processing techniques such as receive equalization. The equalizer taps and other parameters can be tuned to the optimum values in the field via register settings available to the user. However, to find these optimum values, it is necessary to explore the design space. The design space multiplies combinatorially when one considers transmitter parameters and channel design parameters. In addition, the logic block that implements the signal processing function can be quite large — tens of thousands of transistors — making conventional SPICE-like transient simulations with netlist-based IC models impractical. New simulation techniques are needed as well as new types of IC models. In this webcast we’ll explain how channel simulation and IC models based on the emerging IBIS 5.0 AMI flow can solve these challenges.

Webcast 2: Overcome PI Challenges on Perforated Power/Ground Planes

January 19, 2012

First Session: 7AM PT/10AM ET/3PM GMT/16:00 CET

Second Session: 10AM PT/1PM ET/6PM GMT/19:00 CET

Traditional power integrity tools fail when applied to PCBs and packages with heavily perforated power/ground planes because they were built for high layer count boards that can afford the luxury of solid power/ground planes. Thus, they sacrifice generality to gain speed and capacity. In this webcast, we’ll explain a different approach that’s applicable to PI analysis on cost reduced consumer boards whose power/ground planes are perforated with signal traces.

Webcast 3: Introduction to EMI/EMC Challenges and Their Solution

February, 16 2012

First Session: 7AM PT/10AM ET/3PM GMT/16:00 CET

Second Session: 10AM PT/1PM ET/6PM GMT/19:00 CET

In the multigigabit era, passing EMI/EMC specs is increasingly challenging. Discovery of an EMI/EMC failure late in the project can force a recourse to makeshift solutions that add unit cost and delay time to market.

In this webcast, we explain the causes of EMI/EMC and propose a proactive methodology that we dub “Virtual EMI lab.” This methods uses EM simulation to identify and mitigate issues early in the design when many more design options are available. The “Virtual EMI lab” discipline includes both pre-manufacture EM simulations and methodology refinement via post-manufacture co-relation against measured data from EM chambers and EM scans. Our examples include: trace emission from MA/CMD memory, return-current emission on data nets on packages, SSO emission due to Icc(t), and HDMI cable emission due to grounding issues between the connector and the PCB.

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