Lambert Simonovich, founder and president of Lamsim Enterprises Inc., has posted a nice article on the perils of modeling distributed structures (vias in this case) as a single lumped element (a capacitor in this case). The lumped element approximation works if the total delay across the via is much less than the rise time of the edge, but not otherwise. He gives an example of such a model that worked at 3.125 GB/s but which fails at 10 GB/s. The title of the article is PCB Vias Are Capacitive But Not Necessarily Capacitors and Bert uses the distributed and lumped element models in ADS to illustrate his point. Thanks, Bert!
Bert sent me pointers to some other work too. I thought I’d pass those along too: