Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Agilent EEsof India User Group Meetings in December

Posted November 21st, 2012 · Please leave a comment · Seminar

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Posted by Colin Warwick

Here is a link to the program for the Agilent EEsof India User Group Meeting. The meeting is an annual forum where users come together to share their ideas and success, discuss challenges, and interact with application consultants from Agilent Technologies. Our team in India invites you to attend these upcoming events. The dates and locations for the event are as follows:

Monday December 3, 2012 Hotel Le Meridien, Bangalore Note: This is the only stop that has the parallel signal integrity track: click on the program link above.

Wednesday December 5, 2012 Hotel Taj Deccan, Hyderabad

Friday December 7, 2012 Hotel Le Meridien, Chennai

Signal Integrity track (Bangalore stop only)

AP6: Mobile Antenna Lab for Smartphones and Tablets

Anurag Bhargava

Traditional Design of Smartphone/Tablet Antennas (GSM, BT & GPS) depends on cut/paste or trimming of copper-tape antennas on the mechanical model of the Smartphone/Tablet enclosure. This process is time-consuming and produces large OPEX on top of failure to address critical issues such as the coupling of digital noise on the PCB to RF Antennas. As an example, the traditional process maximizes the RF Antenna performance for GSM signals, however, it does not minimize the coupling of LPDDR2/3 running at 1067MB/s to GSM Antenna working in the 900MHz band. Virtual-Mobile Antenna Lab is an innovative process to design multi-band RF Antennas such as GSM & BT & GPS concurrently along w minimization of the coupling of digital noise from critical interfaces such as USB3 (5GB/s with 2.5GHz clock) to the BT Antenna (2.4GHz).

AP7: A Day in the life of a Memory System Architect

Hany Fahmy

Memory architects face a tremendous challenge in the design of a memory channel for each of these applications. They have to find the optimum compromise between peak-bandwidth, power consumption and cost. To do this, successful designers use an advanced workflow and methodology supported by accurate modeling of each component of the memory channel. Unfortunately, one method can’t do it all, so an integrated toolset is required: Trace and via interconnects on PCBs and packages can be modeled quickly and accurately by applying a 3D multilayer full-wave EM solver that uses the method of moments; Connectors are best handled using 3D arbitrary geometry full wave methods such as finite element method (FEM); Cables are best modeled by measurement-based modeling using TDR or VNA measurements; I/O buffers can be modeled either using IBIS, IBIS-AMI or netlist-based models in the time domain; Finally SSO noise generated from the memory devices is a wide-band phenomena that is best handled using time-domain 3DEM tools such as FDTD. The goal is to eliminate the noise on power/ground planes that has deleterious effects such as synchronous switching noise and EMI violations. To comply with such EMI standards as FCC or CISPR it is better to fix the emission by designing the PDN correctly, rather than being forced to use spread-spectrum clocking, because the latter impairs the memory channel performance. Agilent Advanced Design System (ADS) offers a unique, integrated workflow consisting of circuit and channel schematics and simulation as well as 3D multilayer layout and MoM EM solver. In addition, ADS includes a patented convolution engine that lets you add frequency-domain models into a time-domain simulation for eye diagram and BER contour analysis. EMPro extends ADS with 3D arbitrary geometry drawing environment and FEM and FDTD EM solvers.

AP8: Introduction to EMI/EMC challenge and their solution

Hany Fahmy

In the multi-gigabit era, passing EMI/EMC specs is increasingly challenging. Discovery of an EMI/EMC failure late in the project can force recourse to makeshift solutions that add unit cost and delay time to market. In this presentation, we explain the causes of EMI/EMC and propose a proactive methodology that we dub “Virtual EMI lab.” This method uses EM simulation to identify and mitigate issues early in the design when many more design options are available. The “Virtual EMI lab” discipline includes both pre-manufacture EM simulations and methodology refinement via post-manufacture co-relation against measured data from EM chambers and EM scans. Our examples include: trace emission from MA/CMD memory, return-current emission on data nets on packages, SSO emission due to Icc(t), and HDMI cable emission due to grounding issues between the connector and the PCB.

AP9: Efficient End-to-end Simulations of 25G Optical Links

Anurag Bhargava

Optical interconnect provides superior bandwidth that supports communication data rates above 25Gbps. Reliable optical channel analyses require modeling of both electrical and optical components in the system. This paper introduces a novel approach to enable efficient end-to-end optical link simulations based on the IBIS AMI methodology. SERDES are represented by AMI models and the optical channel is modeled with an extension of AMI. Accurate optical models are developed to simulate laser, fiber, photo-detector and amplifier and to capture effects of temperature, optical dispersion, nonlinearity and noise. The approach achieves interoperability between SERDES and optical models and ensures vendor IP protection.

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