Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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High Speed Digital Simulation and Measurement Seminars in the UK: Winnersh, Manchester, Edinburgh: April 19, 25, 26, 2012

Posted April 11th, 2012 · Please leave a comment · Seminar


Posted by Colin Warwick

Updated: April 12, 2012.

Seats are limited so register today for our free full day technical seminar delivered Agilent experts in simulation and measurement.

When digital signals reach gigabit speeds, “unpredictable” becomes the normal state of things. The process of getting your project back on track starts with the best tools and methodology for the job.

This seminar will guide you on how to successfully navigate through today’s high speed technology challenges from early design to prototype validation whilst ensuring compliant designs.

Learn all about Signal Integrity challenges in High Speed Digital links and how you can anticipate and reduce these effects on your design.

Who should attend: Engineers and Managers who are responsible for the design or test validation of complex PCBs and systems

  • 19th April in Winnersh
  • 25th April in Manchester
  • 26th April in Edinburgh


09:00 Registration
09:30 Welcome
10:45 Why Use Simulation Tools for High Speed Signal Channel Design?
11:30 Break
11.45 Measurement Techniques of Serial Signal and Fast Rise Time Signals
13:00 Lunch & Networking
14:00 BGA Probe Case Study: Using Simulation Models to Extend the Reach of Instrumentation
15:00 A Day in the Life of a Memory System Architect
16:00 Conclusion

For further information on topics or registration, please visit us online or call us 0118 9276201 from the UK or + 44 118 9276201 elsewhere.

My UK colleagues look forward to welcoming you to the seminar.

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