Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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High-Speed Digital Design and Verification Seminars

Posted November 5th, 2013 · Please leave a comment · Seminar

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Register today for our High-Speed Digital Design and Verification Seminars. We’re offering them in Santa Clara, California on November 19, 2013 with a repeat on November 20, 2013 and Andover, Massachusetts on December 4, 2013. Full details at the High-Speed Digital Design and Verification Seminar web page.

We’re also running a version that adds a safety critical theme, also in Andover, Massachusetts but on December 5, 2013. Full details of that agenda is at the High-Speed Digital Design and Verification for Safety Critical Applications Seminar web page. Register for that one here.

Hope to see you there!

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