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Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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What On Earth Is Jitter Amplification, and Why Should I Care?

Posted April 1st, 2013 · Please leave a comment · Application Note, Webcast

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Posted by Colin Warwick

My colleague Fangyi Rao will present a live webcast based on the paper he co-authored with Sammy Hindi of Juniper Networks. They won “Best Paper” award for it at the IEEE EPEPS in October 2012.

Dr. Fangyi Rao

Please click the link to register for What On Earth Is Jitter Amplification, and Why Should I Care?

Date: Tuesday, April 09, 2013
Time: 10:00am PT/1:00pm ET
Abstract: High speed digital chip-to-chip link performance is often limited by jitter in the multigigabit per second regime. It is a surprising fact that jitter can actually be amplified by a channel with a low pass filtering characteristic even when the channel is linear, passive, and noiseless. Jitter amplification occurs because jitter adds upper and lower side bands to the desired signal (the “carrier”). In a “low pass’ channel, the carrier is attenuated more than the lower side band so, relatively speaking, jitter amplification occurs. In this webcast we will cover the basics of jitter amplification and show you how to accurately analysis the effect in your system using ADS Channel Simulator.

Click here for a reprint of the award-winning paper Frequency domain analysis of jitter amplification in clock channels

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