Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

Signal Integrity header image 4

Entries Tagged as 'Notice'

PAM-4 Simulation to Measurement Validation

June 29th, 2016 · No Comments · Notice

Share
This DesignCon paper discusses PAM-4 signaling and a new measurement and simulation eco-system. Simulation of PAM-4 signals are done with an IBIS-AMI signal generator, an S-parameter channel model,and remote access software for receiver data recovery. Measured data is from commercially available equipment with specialized waveform processing. Try a free ADS 30-day trial.

[Read more →]

Tags:

Practical Approach for Signal Integrity Analysis of High Data Rate Channels Free One – Hour Webcast in July

June 29th, 2016 · No Comments · Notice

Share
Keysight EEsof EDA’s Tutorials in Signal Integrity webcast series is important to Signal integrity engineers who may not have the time or budget to attend continuing education classes on the latest design tools and techniques. This webcast highlights various technologies used for channel modeling, each with advantages and disadvantages, by utilizing real-world FPGA board routing and […]

[Read more →]

Tags:

Signal Integrity Tips and Techniques Using TDR, VNA and Modeling – Article Reprint.

April 5th, 2016 · No Comments · Notice

Share
Signal integrity (SI) is all about the losses and types of signal degradation that can happen along the path (channel) between a transmitter and a receiver. In a perfect world, transmitter communication would instantaneously be heard at the receiver and with no change in the signal. Read more ow.ly/10bu1g .

[Read more →]

Tags: ·