Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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2016 India Keysight EEsof EDA Design Forum in Less Than a Week!

Posted June 14th, 2016 · Please leave a comment · Seminar

Keysight Technologies cordially invites you to attend the 2016 Keysight India EEsof EDA Design Forum and be a part of the community of RF/MW, EM, baseband system architect and high speed digital application designers in India As the chasm between software developers and hardware engineers yields to a more integrated and collaborative design environment, these communities now work synergistically to accelerate time to market and optimize their designs utilizing both hardware and software.

Register Now.

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Practical Approach for Signal Integrity Analysis of High Data Rate Channels Free One – Hour Webcast in July

Posted June 7th, 2016 · Please leave a comment · Webcast

Keysight EEsof EDA’s Tutorials in Signal Integrity webcast series is important to Signal integrity engineers who may not have time or budget to attend continuing education classes on the latest design tools and techniques. This webcast highlights various technologies used for channel modeling, each with advantages and disadvantages, by utilizing real world FPGA board routing and USB connector design examples. Several state-of-the-art analysis technologies will be highlighted to illustrate end-to-end modeling of high data rate channels that include ICs, PCB interconnects, vias and connectors.

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How do I…? Quick Answers to Your Signal Integrity Questions

Posted June 7th, 2016 · Please leave a comment · Application Note

Check out our 6 Q&A collections, with application notes, that target specific topics such as:

• What are the benefits of ADS for SI? • How to model a high-speed channel? • What is the benefit of S-parameter simulation? • How to get TDR impedance from an S-parameter in ADS? • What are the architectures of the high speed SERDES TX/RX? • How do you analyze impedance of a PDN?

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