Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

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Practical Approach for Signal Integrity Analysis of High Data Rate Channels Free One – Hour Webcast in July

Posted June 7th, 2016 · Please leave a comment · Webcast

Keysight EEsof EDA’s Tutorials in Signal Integrity webcast series is important to Signal integrity engineers who may not have time or budget to attend continuing education classes on the latest design tools and techniques. This webcast highlights various technologies used for channel modeling, each with advantages and disadvantages, by utilizing real world FPGA board routing and USB connector design examples. Several state-of-the-art analysis technologies will be highlighted to illustrate end-to-end modeling of high data rate channels that include ICs, PCB interconnects, vias and connectors.

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How do I…? Quick Answers to Your Signal Integrity Questions

Posted June 7th, 2016 · Please leave a comment · Application Note

Check out our 6 Q&A collections, with application notes, that target specific topics such as:

• What are the benefits of ADS for SI? • How to model a high-speed channel? • What is the benefit of S-parameter simulation? • How to get TDR impedance from an S-parameter in ADS? • What are the architectures of the high speed SERDES TX/RX? • How do you analyze impedance of a PDN?

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My Farewell Posting: How to Model Nonlinear Magnetics in Power Electronics

Posted May 31st, 2016 · Please leave a comment · Video

Signal integrity is all about moving information, but power electronics is all about moving power. So what’s my latest power electronics video doing on a signal integrity blog?

Well, one way of looking at it — and it’s a stretch — is that signal integrity overlaps with power integrity and power integrity starts with the voltage regulation module (VRM) and the VRM is a power electronic circuit.

But the truth is I’ve changed jobs and I’ve handed off the signal and power integrity project here to my esteemed colleagues Heidi Barnes and Stephen Slater. After eight years on signal integrity it was time for a change, so this is my farewell posting to this blog and by way of transition and closure it’s about my debut video on my new project here at Keysight EEsof EDA: power electronics. This blog will continue (and stay on-topic!), with Heidi, Stephen, and Negin Kialoni being your new bloggers, so please stay tuned/subscribed.

When I joined Sanjeev Gupta on the SI project in 2008, Channel Simulation and IBIS AMI was just getting started, DDR didn’t have a BER spec, and EM field solvers couldn’t really solve the largest piece of metal on the board: the power and ground artwork. Bit rates have increased by an order of magnitude or more: USB 2.0 was about 500 Mb/s; USB 3.1 is 5 gigs. Today we have the leading Channel Simulator with IBIS AMI, DDR Bus Simulator, and the application-specific field solvers PIPro and SIPro for PI and power-aware SI respectively. It’s been a fun ride and so thank you to everyone I’ve worked with over the past eight years. If you need any info about VRMs or power electronics, I hope you’ll follow my postings on my LinkedIn blog or ping me at

Best regards,

— Colin

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