Signal Integrity

Power-aware Signal Integrity and EMI/EMC On High-speed Digital Chip-to-Chip Links

Signal Integrity header image 4

Entries Tagged as 'pre-layout'

Webcast: How to Optimize Your SerDes Design During the Pre-layout Phase

September 17th, 2014 · No Comments · Webcast

Share
Live webcast Thursday, September 25, 2014 on stackup and controlled impedance line design using metrics that matter: post-EQ eye metrics.

[Read more →]

Tags: ·